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Raised source/drain (S/D) or raised extension in fully-depleted-SOI (FDSOI) is necessary to boost saturation current, because of increased resistance from the very thin film. We demonstrate that the choice of raising the extension...
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Raised source/drain (S/D) or raised extension in fully-depleted-SOI (FDSOI) is necessary to boost saturation current, because of increased resistance from the very thin film. We demonstrate that the choice of raising the extension versus the S/D, will depend upon the maximum achievable mobility in the structure at a 60 nm physical gate length. We also study the effects of minimum BEOL via spacing on performance, and its consequence on choosing a raised extension or S/D.
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FinFET structures of 10 nm technology node with promising design enhancements like hybrid spacer, raised source and drain extensions, and silicide interfaces have been analysed and compared. Analog figures of merit like drain curr...
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FinFET structures of 10 nm technology node with promising design enhancements like hybrid spacer, raised source and drain extensions, and silicide interfaces have been analysed and compared. Analog figures of merit like drain current, transconductance, intrinsic gain, and transconductance generation factor are determined here. Furthermore, RF figures of merit like cut-off frequency, intrinsic delay, and gate capacitance are analysed. These parameters have been determined at three different temperatures (200 K, 300 K, 400 K) to study the effect of temperature on device performance.
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1 μA/μm). The subthreshold swing (SS) is 100 mV/decade and the drain-induced barrier lowering (DIBL) is 0.8 mV/V, and the Ion/Ioff current ratio is over 108 A/A for Lg?=?1 μm. Using a thin channel structure obtains excellent pe...
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1 μA/μm). The subthreshold swing (SS) is 100 mV/decade and the drain-induced barrier lowering (DIBL) is 0.8 mV/V, and the Ion/Ioff current ratio is over 108 A/A for Lg?=?1 μm. Using a thin channel structure obtains excellent performance in the raised S/D structure. Besides the basic electrical characteristics, the dual-gate structure can also be used to adjust Vth in multi-Vth circuit designs. This study examines the feasibility of using JL-TFTs in future three-dimensional (3D) layer-to-layer stacked high-density device applications.
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A raised Source/Drain (S/D) formation process by Si deposition followed by ion implantation has been developed for deep sub quarter micron MOSFETs with junction-depth under 50 nm. Excellent surface morphology and junction leakage ...
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A raised Source/Drain (S/D) formation process by Si deposition followed by ion implantation has been developed for deep sub quarter micron MOSFETs with junction-depth under 50 nm. Excellent surface morphology and junction leakage characteristic are obtained by CDE (Chemical Dry Etching) Pre-treatment, followed by low temperature UHV annealing at 730 deg. C. Gate-S/D leakage Current is suppressed by the use of Cl_2 pulse irradiation method during the deposition and the dual gate Sidewall-spacer structure.
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We investigate the short-channel performance of trigate silicon nanowire transistors. Drain-induced barrier lowering at a gate length of 25 nm is strongly suppressed by reducing the nanowire width $(W_{rm NW})$ down to 10 nm. We f...
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We investigate the short-channel performance of trigate silicon nanowire transistors. Drain-induced barrier lowering at a gate length of 25 nm is strongly suppressed by reducing the nanowire width $(W_{rm NW})$ down to 10 nm. We found that the parasitic resistance $(R_{rm SD})$ of nanowire transistors is dominated by nanowire-shaped source/drain (S/D) regions under the gate spacer whose resistivity is higher than that in wider regions. We succeeded in significant $R_{rm SD}$ reduction by raised S/D with thin gate spacer whose width is 10 nm. Although the parasitic capacitance $(C_{rm para})$ increases by spacer thinning, $C_{rm para}$ increase is much smaller than $R_{rm SD}$ reduction, and great performance improvement is obtained for a $W_{rm NW}$ of less than 15 nm.
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An air-spacer technology with raised source/drain (S/D) for ultrathin-body (UTB) silicon-on-insultor MOSFETs is developed. The results show that the poly raised S/D can effectively reduce the series resistance and the air spacer c...
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An air-spacer technology with raised source/drain (S/D) for ultrathin-body (UTB) silicon-on-insultor MOSFETs is developed. The results show that the poly raised S/D can effectively reduce the series resistance and the air spacer can effectively reduce the fringing capacitance. The air spacer is particularly useful when combined with high-k gate dielectric. The improved device characteristics are demonstrated experimentally and by extensive two-dimensional device simulation.
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We have successfully fabricated novel sub-10-nm gate-all-around Si nanowire (NW) poly-Si TFTs with raised source/drain structure (GAA RSDNW-TFTs). The Si NW dimension is about 7 $times$ 12 nm. A superior smooth elliptical shape i...
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We have successfully fabricated novel sub-10-nm gate-all-around Si nanowire (NW) poly-Si TFTs with raised source/drain structure (GAA RSDNW-TFTs). The Si NW dimension is about 7 $times$ 12 nm. A superior smooth elliptical shape is obtained, for the first time, in the category of poly-Si NW TFTs through the use of a novel fabrication process requiring no advanced lithographic tools. The GAA RSDNW-TFTs exhibit low supply gate voltage (3 V), steep subthreshold swing $sim$ 99 mV/dec, and high $I_{rm ON}/I_{rm OFF} > hbox{10}^{7} (V_{D} = hbox{1} hbox{V})$ without hydrogen-related plasma treatments. Furthermore, the DIBL of GAA RSDNW-TFTs is well controlled. These improvements can be attributed to the 3-D gate controllability, raised S/D structure, and sub-10-nm Si NW channel. These novel GAA RSDNW-TFTs are, thus, quite suitable for system-on-panel and 3-D IC applications.
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High parasitic S/D resistance is a major obstacle in realizing future generations of CMOS technologies using multiple gate FETs with narrow fins. Reduction of specific contact resistance by selective epitaxial growth of Si in heav...
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High parasitic S/D resistance is a major obstacle in realizing future generations of CMOS technologies using multiple gate FETs with narrow fins. Reduction of specific contact resistance by selective epitaxial growth of Si in heavily doped S/D regions of a multiple gate FET helps with achieving low S/D resistance. This paper addresses integration of low temperature selective epitaxial growth process into multiple gate FET processing. Our experimental results show more than 30% reduction in the parasitic S/D resistance for 16-nm selective epitaxial growth of Si in the heavily doped S/D regions of multiple gate NFETs with less than 20-nm wide fins. A follow up of this work with HfO_2-TiN gate stack shows more than 20% improvement in the drive current at a constant I_(OFF) for 40-nm selective epitaxial growth of Si in the heavily doped S/D regions of multiple gate FETs.
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In this paper, a high-current self-aligned double-channel polycrystalline silicon thin-film transistor (SA-DCTFT) is proposed, demonstrated, and analyzed. This self-aligned device, which includes two channels, a nitride spacer, tw...
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In this paper, a high-current self-aligned double-channel polycrystalline silicon thin-film transistor (SA-DCTFT) is proposed, demonstrated, and analyzed. This self-aligned device, which includes two channels, a nitride spacer, two offset-gated structures, and a raised source/drain (RSD) region, reveals better device performance. In addition, the top and bottom channels of the proposed device are self-aligned, and no extra mask is needed as compared with the conventional double-channel devices. Our experimental results show that the on-current of the SA-DCTFT is about twice higher than that of the conventional structure, and the leakage current and kink effect are considerably reduced simultaneously. Moreover, the device stability, such as threshold voltage shift and current degradation under a high gate bias, is enhanced by the proposed self-aligned double channels, nitride spacer, offset-gated structures, and RSD design. The lower drain electric field of the SA-DCTFT is also benefitted to the device scaling down for better performance.
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The performance of symmetric double-gate MOSFETs with dopant-segregated Schottky (DSS) source/drain (S/D) regions is investigated through a TCAD modeling study and compared to the performance of raised S/D (RSD) MOSFETs. It is sho...
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The performance of symmetric double-gate MOSFETs with dopant-segregated Schottky (DSS) source/drain (S/D) regions is investigated through a TCAD modeling study and compared to the performance of raised S/D (RSD) MOSFETs. It is shown that, while the doped extension region adjacent to the S/D Schottky barrier (SB) improves drive current by shrinking the SB, it is fundamentally limited by its dual role as a heavily doped S/D contact region to improve drive current and as a more lightly doped S/D extension region to reduce BTBT leakage. This restricts the design space for meeting low-standby-power leakage specifications, and so, the RSD structure ends up prevailing both in terms of leakage design space and on-state performance. For high-performance (HP) design, where the higher leakage specification permits heavier extension doping, the performances of optimized DSS and RSD MOSFETs are shown to be very similar. Thus, the optimal S/D design for HP is more likely to be decided by practical considerations such as process integration.
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